Detailed Product Description
CPLD
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The MAX® II family of instant-on, non-volatile CPLDs
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Description: MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP).
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Features:
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Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
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Schmitt triggers enabling noise tolerant inputs (programmable per pin)
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I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI
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Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
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Supports hot-socketing
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Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
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Delivery time: 2WEEKS from distributor
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Payment: T/T in advance
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Issue Time: |
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2024-05-19 |
Expire Time: |
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2025-04-09 |
Keywords: Altera FPGA Complex Programmable Logic Devices