Detailed Product Description
CPLD
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Programmable Logic Device Family
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Description: The EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz..
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Features:
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Open-drain output option in MAX 7000S devices
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Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
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Programmable power-saving mode for a reduction of over 50% in each macrocell
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Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
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44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
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Programmable security bit for protection of proprietary designs
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3.3-V or 5.0-V operation – MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
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Delivery time: 5-7days from distributor
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Payment: T/T in advance
Keywords: Altera FPGA Altera IC